Last time I checked, the EEs had bigger caches, not bigger pipelines...RootHubController wrote:
Easy. The EE has too long a pipeline. The pipeline would be optimal for a 5GHz proc, but instead, it's on a 3.4, and requires redundant instruction sets to accomplish work that could have been handled already.
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the Black Monarch
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NicholasDWolfwood
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Last time I checked, all Pentium 4s had longer pipelines, even the EE.the Black Monarch wrote:Last time I checked, the EEs had bigger caches, not bigger pipelines...RootHubController wrote:
Easy. The EE has too long a pipeline. The pipeline would be optimal for a 5GHz proc, but instead, it's on a 3.4, and requires redundant instruction sets to accomplish work that could have been handled already.
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Scintilla
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Last time I checked, Prescott's pipeline was at least 10 stages longer than Northwood's, so basically some P4s (including the EEs) are more equal than others.NicholasDWolfwood wrote:Last time I checked, all Pentium 4s had longer pipelines, even the EE.the Black Monarch wrote:Last time I checked, the EEs had bigger caches, not bigger pipelines...RootHubController wrote:
Easy. The EE has too long a pipeline. The pipeline would be optimal for a 5GHz proc, but instead, it's on a 3.4, and requires redundant instruction sets to accomplish work that could have been handled already.
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Knowname
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I'd continue this but I'd feel guilty.Scintilla wrote:Last time I checked, Prescott's pipeline was at least 10 stages longer than Northwood's, so basically some P4s (including the EEs) are more equal than others.NicholasDWolfwood wrote:Last time I checked, all Pentium 4s had longer pipelines, even the EE.the Black Monarch wrote:Last time I checked, the EEs had bigger caches, not bigger pipelines...RootHubController wrote:
Easy. The EE has too long a pipeline. The pipeline would be optimal for a 5GHz proc, but instead, it's on a 3.4, and requires redundant instruction sets to accomplish work that could have been handled already.